1. Technical Field
Various embodiments generally relate to a semiconductor device, and more particularly, to a semiconductor device including an error correction code circuit.
2. Related Art
As a voltage applied to a memory cell is lowered and a cell size is reduced, deterioration of soft error tolerance has been problematic. In a semiconductor integrated device using an error correction code (hereinafter, referred to as ECC) circuit for correcting a data error, a circuit technology of adding a parity bit to typical data and correcting a failed bit has been proposed.
That is, after a semiconductor memory device is fabricated, a test is performed to select failed memory cells. One of method for improving the yield of the semiconductor memory device is to provide an ECC function to the semiconductor memory device.
Such an ECC circuit is a circuit that performs a function of detecting and correcting in realtime fail of data, and an additional parity bit is applied to DQ data when the DQ data is transmitted. Thus, the semiconductor memory device checks whether the DQ data and the added parity bit are transmitted according to the prescribed rules and detects a data error.
However, an on-die ECC circuit can correct 1-bit fail but can only detect an error with respect to 2-bit fail. That is, since an address in which the 1-bit fail has occurred is further deteriorated later, an addition failed cell may be generated. In such a case, a data error may occur, resulting in an increase in the number of cells to be replaced with redundant cells in a repair operation.